Kunlin Han

Actively seeking 2024'Spring Full-Time | MSEE@USC | Computer Architecture, OS, Digital Verification, and Digital Design

About Me

Self-motivated and problem-solving student towards a Master in Electrical Engineering at USC (GPA 4.0).

Participated proactively in courses. Also, organized, or even led, small study groups.

Passionate about building bonds with local community.


University of Southern California (USC)

Master of Electrical Engineering; GPA: 4.0/4.0

Dec. 2021 - Dec. 2023

Core Courses:

  • Digital Design (VLSI):
    • CMOS VLSI Circuit Design
    • Asynchronous VLSI Design
    • VLSI System Design
  • Computer Architecture

South China Normal University (SCNU)

Bachelor of Network Engineering; GPA: 3.78/4.0

Sept. 2017 - Jun. 2021

Core Courses:

  • Operating System
  • Computer Network
  • Database System
  • Cryptography
  • Algorithm Design and Analysis
  • Data Structure
  • Object-Oriented Programming (C++)


CS Department, USC

Graduate Teaching Assistant

May 2022 - Aug. 2022

  • Coordinated with Prof. Saty Raghavachary as teaching assistant (course producer) in CSCI-455X Introduction to Programming Systems Design.
  • Presented labs to help students to understand the usage and importance of debugging (GDB) and get an overview of Computer Systems.
  • Held weekly office hours to help students with problems in assignments and labs.

Lab 131, School of Computer Science, SCNU


Sept. 2018 - Jun. 2021

  • Recruited and Communicated members for the Lab
  • Organized and Instructed members to study CS topics: Algorithm (CLRS), Linear Algebra (GSLA), Computer System (CSAPP), Computation Theory (ITOC) and Functional Programming (SICP).


Arm Cortex-A7 MPCore Block-Level Implementation

  • Developed floorplans for Cortex-A7 Core with 32KB L1 DCache and 32KB L1 ICache on 700x840um budget in Innovus using TSMC N28HPC_1P10M_5x2y2z.
  • Completed Clock Tree Synthesis and optimization, which achieves clock tree length around 410ps and clock skew around 40ps.
  • Extracted RC with StarRC, passed timing signoff in PrimeTime and applied ECO from PrimeTime to optimize slack of setup and hold.
  • Cleared DRC and LVS problems in the merged GDSII with Calibre.

Tomasulo Out-of-Order CPU

  • Implemented Issue Unit, 2-stage Dispatch Unit, Re-Order Buffer and FPGA-friendly Copy-Free Check Pointing, which restores FRAT with RRAT.
  • Integrated, synthesized and programmed the overall system on Xilinx Artix-7 FPGA board.
  • Validated the correctness of design with both simulation and on-chip logic analyzer (Chipscope).

512-bit 6T SRAM Array Design

  • Designed and drew layout of 1-bit SRAM cell, row/column decoder, sense amplifier, write driver, precharge circuit, latch and flip-flop with Cadence Virtuoso and GPDK 45nm.
  • Achieved the Read SNM of 210 mV and Write SNM of 395 mV by proper sizing with VDD=1V while minimizing the size of 1-bit SRAM cell.
  • Integrated components into 4 8x16-bit SRAM banks to construct a 512-bit SRAM Array with the area of 2208 $nm^2$ in 2.6 Ghz (cycle time=0.4 ns).
  • Measured the power consumption with Spectre, in which the average consumption for reading is 21.2 fJ, the average consumption for writing is 342 fJ and leakage is around 20 fJ.
  • Validated the correctness of all aforementioned components with vector file in Spectre and cleared DRC and LVS errors.

Extensible Asynchronous SNN Accerlator

  • Designed extensible asynchronous SNN accelerator in SystemVerilog with SystemVerilogCSP library on a 5x5 filter and 25x25 ifmap with stride=1.
  • Implemented fork-join computation module that can calculate part of the overall computation with pre-configured parameter for extensibility.
  • Integrated computation modules with two memory modules, which contain filter map and ifmap respectively, on a mesh network.
  • Verified correctness of computation module and the accelerator separately with timestep=2 in QuestaSim.

Design and Implementation of 5-stage Pipeline Processor

  • Designed and Descibed Data Path Unit and Control Unit for Single-Cycle CPU implementing ADD, SUB, AND, OR, SLT, BEQ, JMP, SW and LW.
  • Designed 32-bit ALU supporting addition, subtraction, logic-and operation and logic-or operation with multiplexer.
  • Resolved problems related to Data Dependency and Early Branching.
  • Utilized RTL in Verilog and Build 5-stage (IF, ID, EX, ME, WB) Pipeline with encoded control signal, Internal Forwarding Register File, Early Branching and optional support for avoiding delay slot.

Full-Custom Design Layout for Arbiter with Multiplier and Divider

  • Designed, Implemented and Drew Layout with the Cadence Virtuoso on GPDK 45nm for a ALU supporing 5-bit multiplication and 10-bit division and a 2-1 Round-Robin-based Arbiter with Multiple and Divide Request.
  • Planned, Routed, Simulated and Checked Correctness for all aforementioned components with Cadence Spectre and Mentor Graph Calibre.

Leadership and Involvement

Hope Center, Reality L.A.


Mar. 2022 - Aug. 2022

  • Sorted, Organized and Shelved food donations
  • Managed and Distributed cooked food by collaborating with other volunteers
  • Coordinated and Helped out in Cleaning utensils

Network Club, SCNU

Vice President of Technical Department

Sept. 2017 - Jun. 2019

  • Managed and Recruited members in Technical Department.
  • Provided technical support to on-campus IT activities, including development and maintenance of school forum, holding CTF competition.
  • Planned and Organized members to write articles around popular computer-related topics, such as resolution of DNS, anti-phishing, to enrich SCNU students’ knowledge.


  • Programming Languages: Python, C/C++, Verilog, VHDL, SystemVerilog, Tcl, Perl, Java, Rust, SQL
  • Libraries: Scrapy, BeautifulSoup, Requests, Pyrogram, Django
  • EDA Tools: Virtuoso, Spectre, QuestaSim, Calibre, Intel Quartus, Xilinx Vivado, Innovus, StarRC, PrimeTime
  • Protocols: AXI, PCIe, MOESI \hspace{\fill} \textbf{Tools:} UNIX, Linux, VIM, Git, Docker, Makefile